editor's blog
Subscribe Now

FLASH Gets Even Smaller

It feels, at first blush, like the conventional wisdom about floating gate cells not having a future at tiny dimensions may have to go the way lots of conventional wisdom goes. On the heels of Kilopass’s 40-nm MTP announcement, Micron and Intel announced NAND FLASH at as low as 20 nm.

So much for not scalable below 90 nm.

The issue here is too much tunneling when the oxides get too thin. It wasn’t supposed to work with oxides this thin. So… was that wrong?

Well, yes and no. According to Micron, “as oxides have gotten thinner, we have had to come up with more complex oxide and dielectric materials.” And they’re not saying more than that. Presumably that means that it’s not trivial and therefore it’s secret. Or maybe it is trivial; even more reason to keep it secret.

Of course, if electrons were tunneling without permission, the result would be decreased data retention. Such leakage gets worse with repeated programming assaults, so the net net of that is that data retention on these memories stays as it always has, but the endurance goes down.

But Micron says they’re playing with one more variable: density. They’re talking about “data retention per byte” as a metric, which is increasing because density is going up faster than endurance is coming down. It sounds from this like they can use the extra density as redundancy to swap out as cells wear out.

So does this mean that those saying you can’t go below 90 nm are being less than honest? Does that mean the conventional wisdom is wrong? Actually, no; there’s one more distinction: as suggested above, it takes special processing to do this. So you can’t simply make this kind of memory cell using a standard logic process. That’s where things break down. So Kilopass is selling IP for integration on chips with other logic (so-called Logic NVM); Micron and Intel aren’t.

More info in their press release

Leave a Reply

featured blogs
Sep 24, 2018
One of the biggest events in the FPGA/SoC ecosystem is the annual Xilinx Developers Forum (XDF). XDF connects software developers and system designers to the deep expertise of Xilinx engineers, partners, and industry leaders. XDF takes place in three locations this year.  Sa...
Sep 24, 2018
For the second year, the Electronic Design Process Symposium (EDPS) took place in Milpitas, having been at Monterey for many years. This was apparently the 25th year EDPS has run. I find EDPS to be a fascinating conference, and I think it is a shame that more people don'...
Sep 21, 2018
  FPGA luminary David Laws has just published a well-researched blog on the Computer History Museum'€™s Web site titled '€œWho invented the Microprocessor?'€ If you'€™re wildly waving your raised hand right now, going '€œOoo, Ooo, Ooo, Call on me!'€ to get ...
Sep 20, 2018
Last week, NVIDIA announced the release of the Jetson Xavier developer kit. The Jetson Xavier, which was developed in OrCAD, is designed to help developers prototype with robots, drones, and other......